1. Field of the Invention
The present invention relates to a noise elimination circuit for eliminating noise signals contained in a pulse signal.
2. Description of the Prior Art
Recently, many developments have been made to a protocol controller, which controls a short distance data transmission, such as in a local network, at a high speed and high reliability between stations. The protocol controller also controls the rules assigned to the stations.
The data transmission system employing the protocol controller utilizes dedicated transmission lines, such as defined by coaxial cables, twist pair lines or optical fibers. Also, the system requires high quality hardware which eliminates noise signals as much as possible so as to improve the high reliability of the data.
For the noise elimination, a noise signal detection and elimination system has been proposed in Japanese Patent Application No. 236580/1983, which is assigned to the same assignee as this case. According to this Japanese Patent Application, 5-bit shift register 1 and decoder 2 defining a 5-bit majority decision circuit, such as shown in FIG. 1, are provided. The operation of the noise signal detection and elimination system of FIG. 1 is as follows.
The 5-bit shift register has an input for receiving data and an input for receiving clock pulses, and five outputs for producing the binary signal carried in each cell. Assuming that a data, such as shown in FIG. 4 waveform (a) is applied to data input and clock pulses, shown in FIG. 4 waveform (b) is applied to clock input. As depicted in waveform (a), data has a noise signal I during its HIGH period and noise signal II during its LOW period. When the first clock pulse is applied, a HIGH is deposited in the first cell of the 5-bit shift register, in response to the step up of the first clock pulse. Thus, five outputs from the 5-bit shift register produces (10000). In this case, majority decision circuit 2 has one 1 and four 0s. The majority is 0 and, thus, circuit 2 generates "0". The output of the majority decision circuit 2 is shown in FIG. 4, waveform (e).
When the second clock pulse is applied, the HIGH in the first cell is shifted to the second cell and a newly obtained HIGH is deposited in the first cell. Thus, 5-bit shift register produces (11000). Since the majority is still "0", circuit 2 generates "0".
When the third clock pulse is applied, the HIGHs in the first and second cells are shifted, respectively, to second and third cells, and a newly obtained HIGH is deposited in the first cell. Thus, 5-bit shift register produces (11100). Now the majority is "1", circuit 2 generates "1". Thereafter, during the HIGH period of the data, majority decision circuit 2 produces a HIGH.
When the noise signal I is received, the output of 5-bit shift register changes from (11111) to (01111) in response to the first clock pulse produced during the period of noise signal I. In this manner, the output of 5-bit shift register changes (01111) to (00111) and further to (00011). If the noise signal I has duration equal to or longer than a 3-clock pulse period, as in the case shown in FIG. 4, majority decision circuit 2 will produce a noise signal for at least one pulse period, as indicated in waveform (e).
Similarly, a noise signal II received during the LOW period of the data will also be produced from majority decision circuit 2.
In order to remove a noise signal having a relatively long duration, it may be accomplished by providing a shift register having a greater number of cell. However, such a shift register results in a high manufacturing cost. Also, even with a greater shift register, a problem described below can not be removed.
When short noise signals appear intermittently, such as noise signals II and III, the majority will change even by one short noise signal. Therefore, when such a short noise signal appears and disappears, the output of majority decision circuit 2 will change between "0" and "1". Thus, the elimination of the noise signals may not be done properly.